Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacers.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation, diffusion doping and activation techniques make transistors on the IC susceptible to a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
As the critical dimensions for transistors are minimized, the total thermal budget (Bt) that the drain and source regions and the semiconductor gate experience becomes more critical. Fundamentally, reducing the thermal budget has several advantages including: (1) more accurate formation of ultra-shallow junctions; (2) formation of ultra-tight dope profiles, such as, profiles for halo implants or retrograded channel implants; and (3) reduction of dopant penetration through the gate oxide and into the gate (e.g., Boron (B) in P-channel MOSFETs). Both shallow source and drain extensions and tight profile pocket regions help to improve the immunity of a transistor to short-channel effects.
Heretofore, conventional processes have reduced thermal budgets for CMOS transistor fabrication by utilizing a rapid thermal annealing (RTA) to heat the substrate. RTA does not require a significant period of time to heat the substrate. Another approach involves a spike RTA which increases the ramping rate of RTA. Nonetheless, the substrate must be exposed to the RTA for a time period of one second or more to appropriately diffuse and activate dopants.
According to conventional processes (e.g., self-aligned CMOS fabrication processes) the polysilicon gate and source and drain regions are implanted (doped) during the same fabrication step. After doping the gate and source and drain regions, the substrate is subject to a heating process which activates the dopant in both the gate and the source and drain regions. However, electrical activation of dopants in the gate requires a relatively high thermal budget (e.g., higher temperature than activation of dopants in the source and drain regions). The higher thermal budget increases the active dopant concentration in the gate which gives the transistor more drive current due to reduced gate-depletion effect. As described above, higher temperatures (higher thermal budgets) increase the susceptibility of the transistor to short channel effects. Therefore, optimizing the heating step for both the gate and for the source and drain regions is difficult.
Thus, there is a need for a method of manufacturing CMOS transistors that does not utilize a single RTA process for the gate and the source and drain regions. Further still, there is a need for transistors that are not as susceptible to gate depletion effect and short channel effects. Even further still, there is a need for an efficient method of manufacturing source and drain regions and polysilicon-based gate conductors.